OpenEP4CE6-C Standard, ALTERA Development Board

Overview

OpenEP4CE6-C is an FPGA development board that consists of the mother board DVK601 and the FPGA core board CoreEP4CE6.

OpenEP4CE6-C supports further expansion with various optional accessory boards for specific application. The modular and open design makes it the ideal for starting application development with ALTERA Cyclone IV series FPGA devices. OpenEP4CE6-C enables you to start your design with the Nios II processor easily and quickly.

What's on the mother board

1. FPGA CPLD core board connector: for easily connecting core boards which integrate an FPGA CPLD chip onboard
2. 8I/Os_1 interface, for connecting accessory boards/modules
3. 8I/Os_2 interface, for connecting accessory boards/modules
4. 8I/Os_3 interface, for connecting accessory boards/modules
5. 8I/Os_4 interface, for connecting accessory boards/modules
6. 16I/Os_1 interface, for connecting accessory boards/modules
7. 16I/Os_2 interface, for connecting accessory boards/modules
8. 32I/Os_1 interface, for connecting accessory boards/modules
9. 32I/Os_2 interface, for connecting accessory boards/modules

10. FPGA expansion connectors
    • FPGA pins are accessible on expansion connectors
    • for connecting SDRAM accessory board
11. LCD interface, for connecting LCD22, LCD12864, LCD1602
12. ONE-WIRE interface: easily connects to ONE-WIRE devices (TO-92 package), such as temperature sensor (DS18B20), electronic registration number (DS2401), etc.
13. Buzzer
14. Joystick: five positions
15. Potentiometer: for LCD22 backlight adjustment, or LCD12864, LCD1602 contrast adjustment
16. Buzzer jumper
17. Joystick jumper
18. ONE-WIRE jumper

The DVK601 supports a wide range of different core boards, therefore, some of the interfaces may be Not-Connected and useless while connecting to certain core board. For instance, while connecting to Core3S250E, the '④ 8I/Os_3' and '⑤ 8I/Os_4' are Not-Connected.

What's on the CoreEP4CE6

1. EP4CE6E22C8N:the ALTERA Cyclone IV FPGA device which features:
   • Operating Frequency: 50MHz
   • Operating Voltage: 1.15V～3.465V
   • Package: QFP144
   • I/Os: 80
   • LEs: 6K
   • RAM: 270kb
   • PLLs: 2
   • Debugging/Programming: supports JTAG
2. AMS1117-3.3, 3.3V voltage regulator
3. AMS1117-2.5, 2.5V voltage regulator
4. AMS1117-1.2, 1.2V voltage regulator
5. EPCS16, onboard serial FLASH memory, for storing code
6. Power indicator
7. LEDs
8. Reset button
9. nCONFIG button: for re-configuring the FPGA chip, the equivalent of power reseting
10. Power switch
11. 50M active crystal oscillator
12. 5V DC jack
13. JTAG interface: for debugging/programming
14. FPGA pins expander, VCC, GND and all the I/O ports are accessible on expansion connectors for further expansion
15. LED jumpers

Photos

OpenEP4CE6-C Development Board

OpenEP4CE6-C Development Board

OpenEP4CE6-C Development Board back view

Mother Board DVK601

FPGA core board CoreEP4CE6

FPGA core board CoreEP4CE6

Connecting to various peripherals

Connecting to 3.2inch Touch LCD

Connecting to LCD12864

Connecting to LCD1602

Connecting to RS232 Board

Connecting to RS485 Board

Connecting to USB UART Board

Connecting to 8 SEG LED Board

Connecting to 8 Push Buttons

Connecting to 5 IO Keypad

Connecting to 4x4 Keypad

Connecting to EEPROM Board

Multi peripherals connected to one interface

Connecting to DataFlash Board

Connecting to Ethernet Board

Connecting to CY7C68013A USB Board

Connecting to NRF24L01 RF Board

Connecting to Micro SD Storage Board

Connecting to VGA PS2 Board

Connecting to SDRAM Board

Connecting to SDRAM Board

Connecting to any accessory board you need

Note: The OpenEP4CE6-C does NOT integrate any programming/debugging function, a programmer/debugger is required.

Examples

The OpenEP4CE6-C FPGA development board comes with various examples codes for the supported peripherals, which give you a quick start to develop your own application.

Debugging/Programming Interface

The OpenEP4CE6-C FPGA development board integrates JTAG interface for programming/debugging.

JTAG Signal Names & Description

JTAG Header Pinout

Development Resources

The User Guide CD includes development resources listed as follow:

• Related Software (Quaters II, NIOS II etc.)
• Demo Code (Verilog, VHDL and NIOS II C)
• Schematic (PDF)
• FPGA Development Documentations (Datasheets etc.)

Wiki: www.waveshare.com/wiki/OpenEP4CE6-C